AXI Bus Interface IP by Uniquify Inc.

SoC IP Provider

Product Description

Uniquify's AMBA AXI protocol is targeted at high-performance and high-frequency system designs. It uses a channel architecture to allow data transfer, command and response signaling to happen simultaneously for greater efficiency.

The controller supports the high performance features of the AXI interface by allowing multiple outstanding read and write commands. The AXI ID is used to identify the data transfer and response signaling for each transfer. The host has full flexibility to control the data transfer to / from the target using the AXI data transfer handshake signals. Multiple writes and reads to different addresses and their associated data are stored and pipelined to enable fast execution by the memory controller.

On write bursts, any combination of write strobes is allowed on every word of the burst.

If the size of the transfer is shorter than the AXI bus width, it is limited to a burst length of 1, but full size transfers can have any burst length. The AXI specification allows burst lengths from 1 to 16. The Uniquify controller not only supports this range, but can extend this to support longer burst lengths if the customer so desires. Though the AXI specification limits the master to not cross 4KB boundaries on a single access, the memory controller places no such restriction and can support page crossings. Please contact Uniquify if support for longer bursts of less than full size transfers is desired. Exclusive access and locked access can be supported based on customer needs.

The AXI write data can be accumulated up to a user defined threshold in the FIFO before being burst on the DDR interface giving the user greater control over the trade-off between latency and efficiency of the write transfer.

The AXI clock domain can be independent of the controller clock domain (faster or slower as necessary). If the 2 clock domains are identical the controller can be configured to use synchronous FIFOs thereby minimizing latency.

The AXI target automatically aligns the transfers to DRAM burst boundaries and generates DRAM data mask enables as necessary. If ECC is enabled, the controller perfoms the necessary read-modify-write operations to update partial DRAM data words since it is necessary to read the data, update only the necessary byte locations and recalculate the ECC before writing the full data word back into the DDR SDRAM.

Response signaling for reads is passed along with the read data itself and indicates if any ECC error was detected (if ECC is supported). Response signaling on writes is used to indicate the completion of the write so that the data could be read back on any port.

AXI Bus Interface IP

Market Segment(s)

• Embedded
• Enterprise
• Home
• Mobile
• Mobile Computing

Companion Processor(s)

• Biometrics
• Communication
• DSP
• Flash
• I/O
• Multimedia

ARM Processor(s)

• ARM7EJ-S
• ARM7TDMI
• ARM7TDMI-S
• ARM720T
• ARM920T
• ARM922T
• ARM926EJ-S
• ARM946E-S
• ARM966E-S
• ARM968E-S
• ARM1020E
• ARM1022E
• ARM1136J-S
• ARM1136JF-S
• ARM1156T2(F)-S
• ARM1176JZ(F)-S
• ARM11 MPCore
• Cortex-A8
• Cortex-A9

System IP

• Interconnect Fabric

Physical IP

• DDR I/O (DDRI/II)

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