Uniquify's AMBA AHB-Lite addresses the requirements of high-performance synthesizable designs. It is a bus interface that supports a single bus master and provides high-bandwidth operation.
1. Compliant to AMBA AHB v1.0 specification. AHB interface data width is 32-bits. All AHB burst types and transfer sizes (8, 16 and 32-bits) are supported.
2. Number of AHB targets and grouping of those targets can be adjusted according to customer requirements.
3. Arbitration policy supports:
a. Bandwidth allocation across groups
b. Bandwidth allocation within each group
c. DDR SDRAM Bandwidth optimization through command re-ordering without violating minimum allocated bandwidth for each agent.
d. Giving priority to requests received earlier compared to requests received later.
4. Each AHB target maintains 2 32-byte read caches. Under certain circumstances both caches can be replenished (such as when an AHB undefined length incrementing burst is seen). Otherwise, the cache that was not used last will be used to fetch the required data.
5. When a write is accepted at the arbiter, the arbiter reports the write address to all AHB targets, and any AHB target that has cached this location will invalidate its cache.
6. There is a command FIFO whose depth is programmable and is used to store multiple outstanding write commands.
7. Data for multiple outstanding write commands can be saved in the data FIFO.
8. Data and command FIFO’s can be asynchronous or synchronous. No relationship is assumed between the 2 clock domains.
9. Configuration bit is provided to choose between big-endian and little-endian bus types.