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Databahn-PCIe is a high-quality design IP product that reduces risk and speeds time-to-market for deploying PCI Express interfaces in silicon. The Databahn PCIe core conforms to the latest PCI-SIG specifications and has been extensively validated with the leading PCIe verification tools (PureSpec, PureSuite). It has also been implemented in production silicon and tested with a wide range of commercial motherboards and adapter cards.
- Integration with ARM Physical IP PCIe PHY
- Compliant with PCIe Specification v1.1 and preliminary v2.0
- Compliant with Intel PIPE Specification v1.86
- Root Complex, Endpoint, Dual Mode (RC/EP)
- Link width support: x1, x2, x4, x8
- Dual Link support for two link operation
- 8-bit or 16-bit PIPE support
- Multi-function support
- Full power management support (Legacy PCI, ASPM, PME, beacon)
- Advanced Error Reporting
- High performance: Low latency, high throughput
- Small silicon footprint, low power utilization
- Highly scalable, pipelined architecture
- Integration-friendly, easily targeted at ASIC or FPGA
- Fully verified by PureSpec VIP and PureSuite Compliance Suite
- Tested against Intel, Nvidia, Broadcom chipsets
- In silicon and customer production
- Complete deliverables for integration, verification, and silicon deployment
Databahn provides chip designers with the ability to configure the optimal PCIe controller IP for power, performance, and gate-count requirements. Robust configurability and state-of-the-art features to effectively insulate SoC designers from fast-changing protocols and details associated with DRAM device technology. Pre-configured Databahn PCIe controller cores are also available to provide customers with off-the-shelf IP pre-designed specifically for consumer, enterprise, and mobile applications.
To find out more about how Databahn fits in your design, evaluate Databahn-PCIE or contact Denali today.