ICs being developed at advanced technology nodes exhibit increased sensitivity to manufacturing variations. A small variation in process will affect layout features that can cause defects in the chip and failures which slow yield ramp and lower mature yields. Investigating these types of defects can take weeks or months of effort in the failure analysis lab.
Tessent Diagnosis is an advanced layout-aware scan test diagnosis tool that performs accurate and high-resolution diagnosis using tester failure data, design netlists, and layout data. Tessent Diagnosis determines the defect’s most probable failure mechanism, logic location, and physical location.
- Performs detailed analysis of devices that
fail manufacturing test
- Layout-aware diagnosis is used to increase
resolution and isolate defects to a specific location
- Effectively identify root cause of manufacturing
- Enable diagnosis-driven yield analysis through
fail log monitoring and high-throughput distributed
- Provides diagnosis-specific ATPG algorithms to
accelerate failure analysis