ARM’s highest performing processor, extending the capabilities of mobile and enterprise computing. Read More...
Avitac provides one-stop physical design services to address the challenges of semiconductor companies who do not have the knowledge or resources that are dedicated in this area. Such design services which include chip implementation from logical to physical domain, are to address all physical, functional and timing issues related to 65nm process and below. Some of the tasks include
- Full Place and Route Services for process 65nm and below
- System-on-Chip (SoC) integration for Mix-signals and Analog/RF blocks
- Time-proven project planning and methodology
- Library and hard macro sanity check
- Floorplanning, block placement, package planning, Input-Output (IO) pad placement and power planning
- Clock-Tree Synthesis (CTS) based on clock skew and data skew balancing requirements
- Routing for timing critical nets, Signal Integrity (SI) aware topology planning
- Physical Verification involving adherence checks for design rules, densities, slotting, antenna rules and Layout-vs-Schematic (LVS) check
- Use of different statistics and design metrics generated through proprietary innovative methods to provide insights about the designs. These methods provide unparalleled enhancements to achieve better end products and quality in services.