Eclypse™ Low Power Solution by Synopsys

RTL (Front End) Tools

Product Description

The Synopsys Eclypse™ Low Power Solution provides a comprehensive, silicon-proven approach to design that is power-aware at every stage of the design cycle, including early architectural and system-level analysis, verification, implementation, and sign-off. Throughout the flow the solution supports the IEEE 1801™ (UPF) language, the industry open standard used to specify power intent. The Eclypse Low Power Solution aims to provide designers with full alignment of technology, methodology, intellectual property, services, and industry standards for low power design.


Advanced Low Power Technology
Building on more than 10 years of low power design experience, the Eclypse Low Power Solution includes key technologies that are critical for low power design including:
• Early architectural-level virtual prototyping, that enables engineers to conduct power analysis and HW/SW development months in advance.
• Multi-voltage simulation, that enables designers to validate the digital portions of their designs while taking into account the effects of multiple voltages and operating modes.
• Power-aware synthesis, which carefully balances area, timing, and power constraints to assure best overall quality-of-results (QoR). Its physically-aware algorithms and techniques assure consistent, high correlation between synthesis and place-and-route, reducing the number of iterations required to achieve success.
• Place-and-route, which takes into account net-switching activity, along with timing and congestion, places design cells while automatically inserting special cells utilized for advanced power management techniques. Cells including isolation, level shifters, retention registers and others are automatically adjusted for size to optimize for best power, area and timing of a multi-voltage design.
• Design for Test, which must be power aware, enables engineers to optimize their designs for testability during manufacturing.
• Timing, power and rail analysis, which are required to ensure that the design meets the initial specifications for power consumption and performance.

Methodology:

The Eclypse Low Power Solution is based on open standards for both methodology and languages, which assures easy integration into existing design flows. Language support includes SystemVerilog, VHDL, SystemC, and IEEE 1801 power language. The Eclypse Low Power Solution includes the Verification Methodology Manual for Low Power Design and Low Power Methodology Manual.

Intellectual Property:

The Eclypse Low Power Solution includes the Synopsys DesignWare® IP Library. Low power optimized IP includes USB, PCIexpress, SaTA, DDR3, XAUI and others.

Services:

Synopsys Professional Services is a team of design consultants with an extensive track record of helping customers complete their cutting-edge low power designs.

Eclypse™ Low Power Solution

Market Segment(s)

• Embedded
• Enterprise
• Home
• Mobile

ARM Processor(s)

• ARM7EJ-S
• ARM7TDMI
• ARM7TDMI-S
• ARM946E-S
• ARM966E-S
• ARM968E-S
• VFP10
• ARM1136J-S
• ARM1136JF-S
• ARM1156T2(F)-S
• ARM1176JZ(F)-S
• ARM11 MPCore
• Cortex-A15
• Cortex-A5
• Cortex-A53
• Cortex-A57
• Cortex-A8
• Cortex-A9
• Cortex-M1
• Cortex-M3
• Cortex-R4
• ARMv8

System IP

• Interconnect Fabric

Physical IP

• General Purpose I/O (Inline / Staggered)
• Register File Memory Compilers
• Specialty I/O (HSTL, SSTL)
• SRAM Memory Compilers
• Standard Cell Libraries

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