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AHB@VIP is the VIP(verification IP) to verify AMBA AHB bus, which is widely used in SOC design. The VIP supports both AMBA 2.0 AHB and AMBA 3.0 AHB-Lite protocols. It provides master, slave and arbiter models. The models can generate constrained random transactions to achieve CRV(Constrained Random Verification) methodology.
It not only generates random transactions, but provides a monitor for users to get generated bus transactions. Users can develop scoreboard or components to measure functional coverage to hook up the port of the monitor. The monitor checks bus protocol as well. The VIP makes developing random-based verification environment very easy.
The VIP follows industry standard, SystemVerilog(IEEE Std. 1800-2005) and OVM(Open Verification Methodology (http:://www.ovmworld.org)) 2.0 guidelines. Users only have to be familiar with the standards, no other languages or methodology are required to use the VIP.
The VIP is configurable thanks to OVM. Users can use the VIP as 'ACTIVE' generator to generate random transactions to verify sub blocks in block level verification, while they can use it as 'PASSIVE' monitor to monitor the bus protocol and cover the generated bus transaction in chip level verification.
Users can write different test 'scenarios' without modifying test 'bench', too.