GenSys(R) by Atrenta Inc.

Product Description

The need for higher design efficiencies in all semiconductor product development has led to an increased focus on IP reuse and platform-based design techniques. The ability to perform comprehensive architectural planning/optimization and communicate the goals of the design to downstream team members with clear specifications and no ambiguity represent substantial competitive differentiation. The goal of these activities is always the same – leverage a design investment across multiple similar socket opportunities, and win those sockets through cost and time-to-market advantages. The GenSys product provides an environment to realize these goals.

The GenSys solution has been developed over more than three years with a leading semiconductor company servicing consumer markets. The goal of this work has been to reduce front-end development effort for SoC platforms and derivative designs by more than an order of magnitude, while also dramatically reducing the level of human error in assembly. To accomplish these goals, Atrenta has developed a product that moves beyond early market concepts of platform-based design as the starting point for a new chip RTL, to a system which fully supports architectural planning and a programmed handoff to back-end design.

GenSys(R)

Market Segment(s)

• Enterprise
• Home
• Mobile

ARM Processor(s)

• Cortex-A53
• Cortex-A57
• ARMv8