Memory Interface Solution by Northwest Logic

SoC IP Provider

Product Description

Northwest Logic's high-performance, silicon-proven, easy-to-use IP cores are specifically designed for use in both ASICs and FPGAs. Each core is available in both source code and netlist formats and is provided with a comprehensive Verification Suite and expert technical support.

Key Features
• Complete solution handling all design, test and bring-up challenges
• Fully silicon validated
• Supports full range of memory configurations (on-board chips,
single DIMM, multiple DIMMs, etc.)
• Provides high bus efficiency
• Minimal latency achieved via parameterized pipelining
• Achieves high clock rates with minimal routing constraints
• Minimal ASIC gate count
• Can be flexibly configured for target application
• Simple, easy-to-use interfaces
• Full run-time configurable timing parameters and memory
settings
• Broad range of ASIC and FPGA platforms supported
• Source code available
• Provided with expert technical support
• IP Customization and Logic, Board, and Software Development
services available

Solution Includes:
Add-On Cores
• Bus Interface Cores
— Support AHB, AXI and other bus interfaces
• VFIFO Core
— Turns a segment of memory into a Virtual FIFO
• Multi-Port Front-End Core
— Provides fully arbitrated, multi-port interface
• Reorder Core
— Provides data coherent request reordering based on priority
and optimal bus utilization
• Read-Modify-Write (RMW) Core
— Handles writing non-aligned bursts into ECC protected
memory
• Error Correcting Code (ECC) Core
— Provides standard DRAM error detection / correction
• Multi-Burst Core
— Breaks extended bursts into multiple native memory
bursts
• Memory Test Core
— Performs a random data and address memory test
• Data Analyzer Core
— Used to capture on-chip signals of interest
• BIST Core
— Provides at-speed Memory Controller Core + DDR PHY
production test

Memory Controller Cores
• Support broad variety of DRAMs including DDR3/DDR2/DDR/
SDR SDRAM, Mobile DDR/SDR SDRAM and RLDRAM II

DDR PHY
• Provides a complete DRAM physical interface
• Integrates with ARM Velocity DDR(I/O and DLL)

Memory Interface Solution

Market Segment(s)

• Embedded
• Enterprise
• Home
• Mobile

ARM Processor(s)

• ARM7EJ-S
• ARM7TDMI
• ARM7TDMI-S
• ARM720T
• ARM920T
• ARM922T
• ARM926EJ-S
• ARM940T
• ARM946E-S
• ARM966E-S
• ARM968E-S
• VFP9-S
• ARM1020E
• ARM1022E
• ARM1026EJ-S
• VFP10
• ARM1136J-S
• ARM1136JF-S
• ARM1156T2(F)-S
• ARM1176JZ(F)-S
• ARM11 MPCore
• Cortex-A8
• Cortex-A9
• Cortex-M1
• Cortex-M3
• Cortex-R4
• SC100
• SC200
• SC300
• StrongARM
• XScale
• Mali55
• Mali-200+GP2
• Mali-400
• Other

System IP

• Interconnect Fabric

Physical IP

• DDR I/O (DDRI/II)
• Standard Cell Libraries

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