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MVSIM with VCS® performs voltage-aware simulation of low power designs using advanced power management techniques.
MVSIM Key Features and Benefits
• Voltage-aware simulation – Enable accurate simulation of power-gating, retention, standby and Dynamic Voltage Scaling (DVS) power-management techniques and finds design bugs in advanced low power designs
• Assertion technology – Combination of automatically generated and user-specified low power assertions based on design and power intent mitigate the risk of undetected bugs and increase verification productivity
• Production-proven support for industry standard IEEE 1801 Unified Power Format (UPF)
MVSIM fits into existing design flows
MVSIM has two modes – the Native Low Power (NLP) mode and the Programming Language Interface (PLI) mode.
MVSIM NLP simulates low power designs natively within VCS. This mode offers high-performance low power simulation for VCS users. MVSIM NLP also adds ease-of-setup and use as well as advanced low power debug capabilities.
MVSIM PLI co-simulates with VCS and other 3rd party simulators through a Verilog Procedural Interface (VPI).
It takes in the same RTL or gate-level netlist representation of the design as VCS in either Verilog or VHDL and accepts the same test bench as VCS (now augmented for power management checks). Additionally, it allows the power intent to be specified in UPF.
MVSIM understands all voltage events and accurately simulates the design to verify all power management functions. MVSIM outputs a log file and an error and warnings report for all violations related to multi-voltage checks.
Unique Value of MVSIM
• MVSIM is truly voltage-aware. It detects bugs when multiple voltages transition simultaneously in a design or as a result of incorrect operation during a voltage ramping up or down
• MVSIM can completely verify voltage-control techniques such as DVS and low VDD standby
• MVSIM has built-in automated low power assertions. These assertions are based on years of low-power verification expertise that have been designed into the tools. The automated assertion feature allows the verification engineers to complete the verification process much faster than requiring the engineer to write test benches and assertions for all potential scenarios for failure and mitigates the risk that the testbenches may overlook a critical condition that may cause a functional failure