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What makes SoC level verification different from block level verification? While block level verification can be performed entirely at the RTL level, the same is not true for SoC level verification.
To ensure thorough testing of SoC designs with an embedded ARM processor, some verification teams have used the processor itself to generate stimulus at the SoC level. However, with today's complex designs employing multiple processors like the ARM Cortex™-A15 MPCore™ and the ARM Cortex-A7 MPCore, using software to verify the hardware is no longer an option.
SoC verification teams may use software to verify the hardware in varying degrees, from compiling and executing a handful of tests in C or assembly, to booting an RTOS and running application layer software. But one thing they can all agree on is that when the inevitable failures occur, they're extremely difficult to debug. Especially when the hardware designers say their RTL is good, and the software developers say their code is fine.
Codelink is a non-invasive connection between a simulation (or emulation) target and a debugging environment. It traces the activity of all processors during simulation (or emulation) for automated off-line debugging. As a result, when failures occur at the SoC level, Codelink reduces debugging time from weeks to hours. And for those using emulation, imagine the cost savings when 90% of your debugging can be performed off-line, freeing up valuable emulation time for more regression runs.
Instant Replay - Simulation (or emulation) runs can be replayed in the same way a Digital Video Recorder (DVR) replays a television program. Features include fast-forward, rewind, slow-motion, single-step, pause, forward play, and backward play. In the same way that a DVR allows the viewer to skip over unwanted commercials, Codelink allows verification engineers to skip over uninteresting simulation (or emulation) activity, to be able to focus in on important activity. A particularly valuable feature is the ability to stop on a failure, and replay simulation (or emulation) in reverse, observing the conditions that lead up to the failure.
Multiple Views - Information important to both software developers and hardware designers is presented to standard debugging environments including waveforms, registers, memory, source code, assembly, output, variables, printf, and more. And hover the mouse over a variable at any point in time, and see the value of the variable displayed automatically.
Synchronized Views - Move the time cursor forward or backward in the waveform window, and see all of the other windows instantaneously track to stay in synchrony. Likewise move the pointer up or down in the source code window, and see all of the other windows remain in synchrony. In this way, verification engineers can instantly keep track of exactly what is going on in the hardware and in the software, to quickly debug their designs.
Simulation Acceleration - As verification teams expand their usage of software to verify their hardware, they can turn to Codelink Turbo to accelerate their simulations. Codelink Turbo uses Instruction Set Simulation (ISS) models to speed up processor activity during simulation by a factor of 100X or more. See below for a list of ARM processor models supported.
Simulation Hot Swapping - Other simulation acceleration technologies replace the design's RTL (or DSM) processors with an ISS model, sacrificing simulation accuracy for speed. Codelink is the only simulation acceleration technology that does not employ this technique. Instead, Codelink adds an ISS model for each processor in the design, and then uses each for its intended purpose. When speed is needed, the ISS model is used. When accuracy is needed, the RTL (or DSM) model is used. Codelink uses patented technology to hot swap between the two models, on-the-fly during simulation, eliminating the accuracy versus speed trade-off.
Any SoC design with embedded ARM processors
ARM Cortex A7
ARM Cortex-R7 1
ARM Cortex M1 1
ARM Cortex-M0+ 1
1 In development
ARM Design Studio 5