FlexNoC Network-on-Chip Interconnect IP by Arteris

Product Description

Arteris FlexNoC™ provides on-chip connectivity for SoC IP blocks implementing any combination of AMBA® AXI™, AHB™, AHB-Lite, APB™, OCP and PIF protocols. It is for SoC interconnects with low latency and high throughput requirements. FlexNoC provides support for the features such as clock domain conversion, QoS, debug visibility and security.

Arteris FlexNoC and ARM IP

FlexNoC is 100% compatible with ARM’s AMBA protocols, e.g. AXI™, AHB™, AHB-Lite, APB™, allowing easy use of ARM Cortex and classic processors, Mali graphics processors, and CoreLink system IP.

Advanced features include:

• FlexMem Memory Scheduler
• On-chip Debug, Tracing, and Statistics Collection
• Multiple Power Domain Management for Dynamic Voltage and Frequency Scaling (DVFS)

Why FlexNoC?

Eliminate Routing Congestion

Arteris NoC IP reduces routing congestion by taking advantage of variable link widths and packetization to selectively reduce the number of wires required to meet system throughput and latency constraints.

Whether you are using AMBA AXI3, AXI4, AHB, APB, OCP, PIF or a proprietary protocol, Arteris FlexNoC IP reduces the number of wires by nearly one half, resulting in fewer gates and a more compact chip floor plan.

Ease Timing Closure

Timing closure is simplified by allowing the designer to easily and precisely place pipelines/register slices at specific locations in the interconnect to resolve timing issues. This means timing issues found late in the design cycle can be resolved without having to modify the SoC netlist or re-architect the interconnect.

Reduce Power Consumption with Clock Gating and Frequency / Voltage Domains

FlexNoC includes support to turn of the clocks of IPs that are not being used. Addition options are available for more advanced clock gating, power domain, and dynamic frequency and voltage scaling (DVFS) capabilities.

Advanced Quality of Service

FlexNoC includes Quality of Service features out of the box that propagates master / initiator QoS information (such as AXI QoS information) through the interconnect and to the target.

This end-to-end QoS solution is for on-chip data flows that must meet concurrent bandwidth and latency requirements from the initiator, through the interconnect, and then through the memory controller.

Automated Verification for Lowest Risk

In addition to RTL and the three levels of SystemC TLM 2.0 models provided in FlexExplorer, FlexNoC includes the FlexVerifier Automated Test Environment (ATE) and the FlexVerifier VMM verification environment.

FlexNoC Network-on-Chip Interconnect IP

Market Segment(s)

• Embedded
• Enterprise
• Home
• Mobile
• Mobile Computing

ARM Processor(s)

• ARM7TDMI
• ARM7TDMI-S
• ARM920T
• ARM922T
• ARM926EJ-S
• ARM940T
• ARM946E-S
• ARM966E-S
• ARM968E-S
• ARM1020E
• ARM1022E
• ARM1026EJ-S
• ARM1136J-S
• ARM1136JF-S
• ARM1156T2(F)-S
• ARM11 MPCore
• Cortex-A15
• Cortex-A8
• Cortex-A9
• Cortex-M0
• Cortex-M1
• Cortex-M3
• Cortex-M4
• Cortex-R4
• ARMv4
• ARMv5
• ARMv6
• ARMv7
• XScale
• Mali-400
• Mali-T604

System IP

• Debug
• Interconnect Fabric
• Level 2 Cache Controller
• Memory Controller

Physical IP

• DDR I/O (DDRI/II)