DSP Cores by CEVA, Inc.

SoC IP Provider

Product Description

CEVA-X™:
The CEVA-X family of cores is based on CEVA's latest pioneering DSP architecture. This architecture offers best-in-class performance, scalability, and lowest cost-of-development for DSP deployment

CEVA-X1641™:
CEVA-X architecture compliant core, fully compatible with CEVA-X1620 & CEVA-X1622 DSP’s
32 bits programming model
Nine stages non interlocked pipe line
Quad -MAC Fixed Point
- 16 X 16 bits
- 32 X 16, 32 X 32 emulated
24 orthogonal accumulators
High level parallelism
- 8-instruction VLIW architecture
- 16 SIMD operations per cycle
Up-to 4G byte addressable memory space
Compact code utilizing mixed 16/32 bits instructions
Integral RISC oriented instruction set applicable for protocol
stacks, control code
Integrated, configurable memory architecture
- 64/96/160 KB TCM and cache
- 64Kb/128Kb Data TCM
- DMA Controller

CEVA-X1620/2™:
Silicon Proven, CEVA-X architecture compliant core
32 bits programming model
Nine stages non-interlocked pipeline
Dual MAC fixed-point
- 16 X 16 bits
- 32 X 16, 32 X 32 emulated
High ILP (Instruction Level Parallelism)
- 8-instruction VLIW architecture
- 16 SIMD operations per cycle
Compact code utilizing mixed 16/32 bits instructions
Up-to 4G byte addressable memory space
Integral RISC oriented instruction set applicable for protocol
stacks, control code
Integrated, configurable memory architecture
- 64KB program TCM and cache | 64/128KB Data TCM | DMA
Controller
Plug and play peripheral subsystems, CEVA-XS1100, CEVA-XS1200
Broad offering of video and audio software available

CEVA-TeakLite-III™
Third generation CEVA-TeakLite Architecture
- Backward assembly compatible to CEVA-TeakLite and
CEVA-TeakLite-II
High performance, Low-Cost:
- 350 MHz @ TSMC 90nm/G
- 0.54 mm² @ TSMC 90nm/G
True 32-bit DSP with RISC attributes:
- Single 32 x 32 bit MAC unit
- Dual 16 x 16 bit multipliers
- 32-bit register bank
- 64-bit data memory bandwidth
- 4GB address space
High code density: 16-bit + 32-bit instructions
Viterbi & FFT Acceleration:
- 2 cycles per ACS / butterfly

CEVA-TeakLite-II™
Successor of CEVA-TeakLite
- Binary compatible to CEVA-TeakLite and CEVA-Oak DSP cores
16-bit Fixed Point Single-MAC DSP core
High code density (16-bit instructions only)
High performance, Low-Cost, Low Power
- 245 MHz @ TSMC 90nm *
- 0.25 mm² @ TSMC 0.13um **
- 0.09 mA/MHz in a typical DSP application

CEVA-TeakLite™
16-bit Fixed Point Single-MAC DSP core
Provides general purpose CPU functions
High code density
- Only 16-bit instructions
High performance, Low-Cost, Low Power
- 170 MHz @ TSMC 0.13um *
- 0.4 mm² @ TSMC 0.13um **
-0.09 mA/MHz in a typical DSP application
Binary-compatible to CEVA-Oak™ DSP core
Backed up by extensive library of CEVA & 3rd party software

DSP Cores

Market Segment(s)

• Embedded
• Mobile

Companion Processor(s)

• Communication
• Multimedia

System IP

• Interconnect Fabric

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