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The Bluespec AzureIP bus fabric libraries enable modelers and designers to quickly and correctly create and connect to AMBA AXI and AXI interfaces and channels.
Instead of designing IP for a specific bus type, Bluespec's bus transactors provide support for different bus types, AHB, AXI and OCP-IP, from a single transactional interface. Design IP once, then interface quickly to different bus interconnects and network-on-chip (NOC) protocols. Fully synthesizable while preserving low latency design.
Terrific for IP implementation, but also great for emulation and FPGA prototyping in verification and software prototyping environments.
At the heart of Bluespec's bus fabric IP offering is a unique Transaction Level Modeling (TLM2) bus payload data structure and protocol. This generic representation supports multiple bus protocols (AXI, AHB, and even OCP) and is based on OSCI's TLM 2.0 specification. Use of the TLM2 representation allows customers to work with bus interactions on a transaction level, whether for high-level modeling or efficient hardware implementation. The details of each bus-specific signaling protocol are encapsulated within the library building blocks, eliminating the need to be re-designed and re-verified each time a design includes channels or interfaces based on that protocol. Each package component represents a design template, which is automatically transformed by the Bluespec compiler into a specific, highly efficient instantiation, parameterized and optimized to the specific application context of each use. Unused capabilities are automatically removed, saving power and area as compared to the results that can be achieved using more traditional hardware IP, producing higher quality results in less time.
Included in the library are:
* AXI bus master/slave interfaces
* AHB bus master/slave interfaces
* TLM2 bus payload data structure and protocol modules
* Fully synthesizable, high-level Get/Put transactional interfaces for interfacing to IP
Key benefits include:
* Enables modeling and design of master and slave devices without having to worry about bus details
* Promotes fast and correct design exploration
* Future-proofs your designs to support multiple different buses. For example, design for AHB today and easily adapt to AXI in the future
* Synthesizes to low latency, area-efficient, optimized gate-level netlists