Sidense OTP memory IP is based on a patented, area-efficient antifuse cell: 1T Fuse(TM) employing gate oxide breakdown as a programming mechanism. Available in a standard CMOS process, Sidense macrocells do not require any additional mask layers or process steps and provide an alternative to mask ROM, eFuses and Flash memory in many applications.
The SLP macrocell is designed to minimize active and standby power consumption. The macrocell integrates three read operating modes (Single-ended, Differential and Redundant), and several test modes to simplify production testing and programming verification. Multiple macrocells can be tiled together to form larger OTP modules.
The SLP macrocell is offered with an optional Integrated Power Supply (IPS) macrocell. The IPS generates the read and programming voltages from a 3.3V (VCC) supply.
SiFuse Features include:
• Densities from 128 bits to 256 Kbits
• I/O Widths from 8 to 128 bits
• Optional Integrated Power Supply (IPS)
• Ultra low read power consumption
• Built-in word-line test mode
• Built-in bit-line test mode
• Very high reliability
• Serial or high speed parallel programming
• Built-in sense amplifier test mode
• Built-in cell margin modes for programming verification
• > 20 years data retention
• Mask ROM option for high-volume programming
• Incremental in-field programming and locking function
• Process Specific Datasheet
• Design Models (Verilog, .LIB)
• Integration & Application Notes
• Hard Macro placement file in LEF format
• GDS Database
• LVS Netlist
Available from all top-tier foundries and selected IDMs.
Please inquire for availability to latest foundries and nodes.