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Sidense's SiPROM OTP IP is based on a patented, area-efficient antifuse cell – 1T Fuse(TM) – employing controlled gate oxide breakdown as a programming mechanism. Available in a standard CMOS process, Sidense macrocells do not require any additional mask layers or process steps and provide an alternative to mask ROM, eFuses and Flash memory in many applications.
The reduced size of the single transistor bit-cell results in better yield, higher security, improved reliability and lower overall product cost.
SiPROM products are silicon proven and are available at all top-tier foundries and selected IDMs. The IP is available in standard-logic CMOS processes at 130nm, 110nm, 90nm, 65nm, and 55nm and is scalable to 28nm and below.
• Densities from 4 Kbits to 512 Kbits per macro
(multiple macros can be used for higher memory capacity)
• I/O Widths to 128 bits
• Read Access Times down to 10ns
• Multiple banks programmable in parallel
• Built-in charge pump for in-field programming
• Built-in row redundancy
• Built-in OTP Boot Block
• Very high reliability
• Serial or high-speed parallel programming
• Built-in Charge pump for field programming
• > 20 years of data retention
• Sector lock function
• Mask ROM option for high-volume programming
• Incremental in-field programming and locking function
• Testing algorithm to test each bit, before and after programming
• Process -specific Datasheet
• Design Models (Verilog, .LIB)
• Integration and Application Notes
• Hard Macro placement file in LEF format
• GDS Database
• LVS Netlist