ARM-Cadence® Encounter® Reference Methodology by Cadence Design Systems

Product Description

ARM-Cadence Encounter Reference Methodology
Optimized RTL-to-GDSII implementation flow for ARM synthesizable processors

With the widespread use of ARM synthesizable processors for leading-edge designs, customers want integrated solutions to achieve highest quality-of-silicon with the fastest design cycle. ARM licensees need the predictability and time-to-market advantages of a hardened processor with the flexibility of a fully synthesizable implementation. By streaming the implementation of ARM synthesizable processors, the ARM-Cadence Encounter Reference Methodology provides this capability and is a key deliverable of the ongoing collaboration between ARM and Cadence.

The ARM-Cadence Encounter Reference Methodology is a proven implementation flow that delivers a powerful, deterministic, and rapid route from RTL to GDSII for ARM synthesizable processors. This increases the productivity of the design team and reduces time-to-silicon with predictable performance, power and area results. In addition, by providing accurate abstract models, the methodology enables licensees to deploy the ARM processor as a library component for System-on-Chip (SoC) integration by end users.

This RTL-to-GDSII flow is based on the Cadence Encounter digital IC design platform. The Cadence tools supported in the ARM-Cadence Encounter Reference Methodology include Encounter RTL Compiler, Encounter Digital Implementation System (EDIS), QRC Extraction, Encounter Timing System, Encounter Power System, Encounter Test and Encounter Conformal Logic Equivalence Checker.

Low Power flows are available for ARM processors that support advanced low power techniques including logic isolation, state retention and power gating using the CPF driven functionality in Encounter RTL Compiler and Encounter Digital Implementation System. Conformal Low Power is used to verify the low power intent.

ARM and Cadence are committed to maintaining Reference Methodologies in line with customer demand driving tool enhancements by Cadence and new synthesizable processors from ARM.

ARM-Cadence® Encounter® Reference Methodology

Market Segment(s)

• Embedded
• Enterprise
• Home
• Mobile
• Mobile Computing

ARM Processor(s)

• ARM7EJ-S
• ARM7TDMI-S
• ARM926EJ-S
• ARM946E-S
• ARM966E-S
• ARM968E-S
• ARM1026EJ-S
• ARM1136J-S
• ARM1136JF-S
• ARM1156T2(F)-S
• ARM1176JZ(F)-S
• ARM11 MPCore
• Cortex-A15
• Cortex-A53
• Cortex-A57
• Cortex-A8
• Cortex-A9
• Cortex-M0
• Cortex-M1
• Cortex-M3
• Cortex-R4
• ARMv8

System IP

• Interconnect Fabric
• Memory Controller

Physical IP

• DDR I/O (DDRI/II)
• General Purpose I/O (Inline / Staggered)
• Register File Memory Compilers
• Specialty I/O (HSTL, SSTL)
• SRAM Memory Compilers
• Standard Cell Libraries