ArraytestMaker by Genesys Testware
RTL (Front End) ToolsProduct Description
ArraytestMaker helps IC designers increase the yield and quality of nanometer memories. It automatically embeds test, diagnosis and repair circuits as an RTL wrapper around each memory in the design. RTL circuits to control and monitor the embedded test, diagnosis and repair wrappers for all the memories in a design are then added to the top-level of the design. The solution has been validated by Genesys with ARM Artisan ProcessPerfect, FlexRepair, Advantage and Metro memory compilers. The validation process involves generating all canonical configurations for each memory compiler within the family, generating test, diagnosis and repair RTL circuits for them, verify fault-free and faulty operation of the memory through simulation, synthesize to gate level using ARM standard cell library, and verifying the correct operation of gate level test, diagnosis and repair circuit for memories. Application notes documenting the validation process for each memory compiler family is available at http://www.genesystest.com . The top-down automated design flow has been validated with Synopsys, Cadence and Magma design implementation systems using ARM Artisan standard cell libraries.
Market Segment(s)
- Embedded
ARM Processor(s)
- Cortex-A53
- Cortex-A57
- ARMv8
Physical IP
- Register File Memory Compilers
- SRAM Memory Compilers
- Standard Cell Libraries
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