ARM AND CPU-BASED ARCHITECTURES
YOGITECH, member of the ARM Approved Design Center Program, has a long track record on ARM system such as system architecture and partitioning, system verification and debug at board level, design of AHB/APB/AXI devices, use of ARM’s PrimeCells, front-to-back
and back-end support, use of ARM RVDS developer suite, MultiICE, ARM Emulator boards, development of ARM-based firmware. Yogitech has brought many ARM projects to tape out, such as ARM7-based systems for automotive applications and ARM9-based SoC for ADSL modems. YOGITECH's expertise in CPU-based architectures includes other popular embedded procesors, DSPs emulation boards of off-the-shelf MCUs such as NEC, Freescale and others.
TESTABILITY, RELIABILITY AND FAULT ROBUSTNESS
YOGITECH's SoC design team has a distinguishing competency in Design-for-Robustness and a deep knowledge of Testability and Reliability issues, of standard requirements such as IEC 61508,
a consolidated experience in BIST, BISR, IEEE 1149.1 design and a well defined design flow, including FMEA most advanced DfT techniques and tools.
SoC DESIGN FLOW
YOGITECH's SoC flow supports both Verilog, VHDL, SystemC and SystemVerilog descriptions starting from system specification and partitioning until the tape-out, passing from RTL Design and Verification (Static and Dynamic), synthesis techniques for low-power or very high-speed applications, Physically aware synthesis, Static Timing Analysis, Formal Verification, fast prototyping with FPGA, Test Insertion and ATPG, Advanced Place&Route with IPO and signal integrity. Testability, Reliability analysis and Functional Verification are applied during the entire flow. The design flow takes into account the use of EDA tools from leading providers such as Cadence, Mentor and Synopsys. YOGITECH's track record include SoC taped-out with technologies from 0.13um to 0.35um, and experiences in the ultradeep sub micron range such as 90nm.