PowerCentric by Azuro, Inc.

Product Description

PowerCentric is a complete CTS solution that fits easily into all major design flows. It's been proven on many customer tapeouts that include 5 of the world’s top 10 semiconductor vendors and has succeeded on chips with over 2 million instances, dozens of voltage regions and over 100 clocks in a single design. PowerCentric applies innovative technology to achieve the following major benefits:
- Up to 40% clock power savings over traditional CTS
- Typically 30% less clock buffer area
- An average of 10% smaller insertion delay
- Tighter achievable skew margins
- Concurrent multi-corner CTS and multi-mode CTS
- Interactive visualization techniques to help manage complex clock networks

CTS Driven by Design Objectives
Azuro implements CTS as an optimization step driven directly by your true design objectives: timing, power and area. PowerCentric can achieve a more optimal clock structure because it understands the precise timing/power/area/routability consequences of the choices it makes. PowerCentric integrates full-chip STA, full-chip dynamic & leakage power analysis, global routing and RC extraction engines together with the CTS algorithms.

PowerCentric combines CTS and post-CTS optimization into a single, unified optimization step that produces lower power clock networks with significantly less area and better timing results for clock skew, clock cap, insertion delay and slew.

Low Power CTS
PowerCentric lowers your clock power consumption by up to 40% without any impact on the clock timing or the clock area. It's gate-level Advanced Clock Gating (ACG) capability detects and implements many more gating opportunities than can be found at the RTL level. PowerCentric’s integrated timing optimization ensures the timing correctness of the clock gate enable logic. The ACG clock-gating technology is also activity aware and can generate full chip activity, or it can accept VCD/SAIF activity files.

PowerCentric CTS is fully multi-voltage capable with support for UPF/CPF type constraints across dozens of voltage regions.

Multi-Corner, Multi-Mode CTS
PowerCentric’s concurrent timing algorithms make it possible to build a clock tree which meets setup and fixes hold timing across multiple corners and modes in the presence of OCV derates. Timing and power consumption are analyzed and optimized across the various modes and corners.

Manage Clock Complexity
PowerCentric eliminates the need for complex clock tree configuration scripts. The integration of post-CTS optimization together with the actual clock tree building avoids time-consuming iterations between CTS and optimization.

PowerCentric's unique visualization capabilities let you display and browse your clock tree while highlighting slack, activity, slew, timing reports and many other characteristics. This has proven invaluable to resolve the most complex clock tree problems quickly and efficiently.

PowerCentric

Market Segment(s)

• Embedded
• Enterprise
• Home
• Mobile

ARM Processor(s)

• ARM7EJ-S
• ARM7TDMI
• ARM7TDMI-S
• ARM720T
• ARM920T
• ARM922T
• ARM926EJ-S
• ARM940T
• ARM946E-S
• ARM966E-S
• ARM968E-S
• VFP9-S
• ARM1020E
• ARM1022E
• ARM1026EJ-S
• VFP10
• ARM1136J-S
• ARM1136JF-S
• ARM1156T2(F)-S
• ARM1176JZ(F)-S
• ARM11 MPCore
• Cortex-A53
• Cortex-A57
• Cortex-M3
• SC100
• SC200
• SC300
• ARMv8
• StrongARM
• XScale

Physical IP

• Register File Memory Compilers
• SRAM Memory Compilers
• Standard Cell Libraries