Verdi Automated Debug System by SpringSoft (acquired by Synopsys)

Product Description

The Verdi™ Automated Debug System is an advanced solution for debugging your digital designs. It provides powerful technology to help you:

• Comprehend complex and unfamiliar design behavior

• Automate difficult and tedious debug processes

• Unify diverse and complicated design environments




Increase Design Productivity
Verdi lets you focus on tasks that add more value to your designs by cutting your debug time, typically by over 50%. Verdi's technology:

-Automates behavior tracing with its unique behavior analysis technology
-Extracts, isolates, and displays pertinent logic in flexible and powerful design views
-Reveals the operation of and interaction between the design, assertions, and testbench

Standard Features:

-Waveforms - Full-featured waveform package supports traditional display and analysis of activity over time
Waveform Comparison Engine - Powerful comparison engine isolates differences between two Fast Signal Database (FSDB) files
-Source code browser - Active source code display provides easy traversal of source and hierarchy
-Schematics - Flexible schematics and block diagrams display logic and connectivity using familiar symbols
-State machine diagrams - Intuitive bubble diagrams reveal the operation of finite state machines


Advanced Features:

-Automatic tracing of signal activity - Powerful behavior analysis technology reduces manual tracing of activity across many clock cycles
-Temporal flow views - Combined display of time and structure provides rapid understanding of cause/effect relationships
-Assertion-based debug - Integrated support for assertions enables quick traversal from assertion failure to related design activity
-Testbench debug - Specialized support for automated testbench environments provides seamless tracing of cause/effect across the design/testbench boundary


Languages and Methodologies:

-Design components described in Verilog, VHDL, and SystemVerilog
-Automated testbench environments using e, Vera, and SystemVerilog testbench
-Assertions using PSL, OVA, and SystemVerilog Assertions (SVA)
-System-level design using SystemC and transactions (when used with Springsoft' nESL™ product)

The Verdi Automated Debug System is a robust and sophisticated system that significantly raises your design productivity by radically reducing the time and effort required to comprehend the behavior of complex designs. Verdi's open architecture and extensive integration unify your verification environment while its powerful automation technology allows you to spend more time designing and less time debugging so you can keep your designs on schedule.

Verdi Automated Debug System

Market Segment(s)

• Embedded
• Enterprise
• Home
• Mobile

ARM Processor(s)

• ARM7EJ-S
• ARM7TDMI
• ARM7TDMI-S
• ARM720T
• ARM920T
• ARM922T
• ARM926EJ-S
• ARM940T
• ARM946E-S
• ARM966E-S
• ARM968E-S
• VFP9-S
• ARM1020E
• ARM1022E
• ARM1026EJ-S
• VFP10
• ARM1136J-S
• ARM1136JF-S
• ARM1156T2(F)-S
• ARM1176JZ(F)-S
• Cortex-A53
• Cortex-A57
• SC100
• SC200
• SC300
• ARMv8
• StrongARM
• XScale