ARM-Synopsys Implementation Reference Methodology by Synopsys

Product Description

Through the results of technical collaborations between ARM and Synopsys, ARM® synthesizable processor cores have become as easy to deploy as a compiled RAM cell. ARM and Synopsys co-develop and update the ARM and Synopsys Implementation Reference Methodology (iRM), a proven methodology built from the best practices for the implementation of high-performance, low-power ARM processors with Synopsys’ latest tools, flows and solutions. This ARM and Synopsys iRM is a fully automated, production proven implementation flow based around Synopsys’ Galaxy™ Implementation Platform and Synopsys’ Eclypse Low Power Solution, and is fully portable across multiple silicon technologies and process nodes.

Key Productivity Features and Benefits
The ARM and Synopsys iRM enables ARM partners to harden ARM synthesizable processors quickly with superior quality of results (QoR). It streamlines the process used by designers to target ARM processors to their chosen silicon technologies by reducing the time required to harden and model the core from months to a few days. The iRM also enables system-on-chip (SoC) designers to integrate their application-specific cores without having to re-verify – by using industry-standard views and models created accurately during the core hardening process. Designers can use the iRM with their own choice of silicon process libraries or take advantage of the included ARM Physical IP reference libraries. The assurance and speed of the iRM provides ARM’s partners flexibility, predictability and a time-to-market advantage with no compromise in system performance.

Advanced High-performance, Low Power Design Techniques
The ARM and Synopsys iRM takes full advantage of Synopsys’ latest advanced technologies, including Synopsys’ Design Compiler Graphical extended topographical technology and IC Compiler’s power-aware placement for the latest ARM processors, ARM Physical IP libraries and Power Management Kits (PMKs), plus top-down multi-voltage (MV) Dynamic Voltage, Frequency Scaling (DVFS) support for ARM family of IEM technology-enabled processors. Synopsys latest tool support includes:-
• Design Compiler® Graphical, DesignWare® Library, DFT Compiler, DFT MAX and Power Compiler™ for RTL synthesis
• Formality® for formal equivalent checking
• IC Compiler for hierarchical design, power planning and physical implementation
• PrimeRail for full-chip power network analysis
• PrimeTime® PX, PrimeTime SI, PrimeRail and Star-RCXT™ for design integrity checking and sign-off
• TetraMAX® for ATPG

Availability
The ARM and Synopsys Galaxy iRM is an integral part of the standard IP distribution from ARM for all synthesizable processors, including the new ARM Cortex™-A9 single and multicore configurations, and are available to all qualified ARM licensees. Please contact your ARM Partner Manager for more details.

ARM-Synopsys Implementation Reference Methodology

Market Segment(s)

• Embedded
• Enterprise
• Home
• Mobile

ARM Processor(s)

• ARM7EJ-S
• ARM7TDMI-S
• ARM926EJ-S
• ARM946E-S
• ARM966E-S
• ARM968E-S
• ARM1026EJ-S
• ARM1136J-S
• ARM1136JF-S
• ARM1156T2(F)-S
• ARM1176JZ(F)-S
• ARM11 MPCore
• Cortex-A53
• Cortex-A57
• Cortex-A8
• Cortex-A9
• Cortex-M1
• Cortex-M3
• Cortex-R4
• ARMv8

System IP

• Interconnect Fabric

Physical IP

• General Purpose I/O (Inline / Staggered)
• Register File Memory Compilers
• Specialty I/O (HSTL, SSTL)
• SRAM Memory Compilers
• Standard Cell Libraries