Synopsys - AMBA On-Chip Bus IP, Peripherals & Verif...

Synopsys

AMBA On-Chip Bus IP, Peripherals & Verification IP

RTL (Front End) Tools

Product Description

The Synopsys DesignWare IP solutions for AMBA® Interconnect include a comprehensive set of synthesizable and verification IP and an automated method for subsystem assembly with the coreAssembler tool. The DesignWare IP is fully compatible with the ARM® AMBA® 2.0 and AMBA 3 AXI™ protocols allowing flexible system architectures to fully support design requirements. The configurable IP architecture coupled with the automated assembly tool reduces the complexity of designing next-generation AMBA-based subsystems and significantly improves productivity for faster time to results.

The Hybrid architecture feature of the DesignWare Interconnect Fabric for AMBA 3 AXI enables the combination of dedicated high performance channels with lower performance shared channels. By eliminating redundant logic and wires designers are able to realize lower area, power and reduced routing congestion. The hybrid architecture provides a balance between area, performance and power which can be immediately utilized in native AMBA 3 AXI based design or in designs transitioning from AMBA 2.0 AHB™.

Synthesizable IP Highlights

Support for AMBA, AMBA-Lite and multi-layer AMBA
- Configurable IP consisting of Bus IP, system components and peripherals enable rapid development of AMBA-based SoCs
- Deliverables including synthesizable RTL, synthesis scripts, simulation test bench, databooks, application notes and C/HDL header files for software drivers

Synthesizable IP Components

- AMBA 3 AXI Bus Interconnect Fabric with Hybrid architecture
- AMBA 2.0 AHB, AMBA 2.0/3.0 APB™ Bus Interconnect Fabric

- Generic Interface Modules
- Master/slave for AMBA 3 AXI
- AHB-AHB, AXI-AHB, AXI-AXI Bridges
- Multi-layer Connection Matrix
- SDR/SRAM Memory Controller
- DMA Controller
- Interrupt Controllers
- Remap & Pause
- General Purpose I/O
- I2C, I2S
- Real Time Clock
- Synchronous Serial Interface
- Timer
- UART
- Watchdog Timer

Verification IP Highlights

- AMBA 3 AXI Assured Logo certified
- Support for AMBA, AMBA-Lite, multi-layer AHB
- Supports directed and randomized test methodologies
- Automatically generate transactions using Constrained Random Verification techniques
- Programmable notifications allow for self-checking, adaptive testbenches
- Protocol checking and transaction logging
- Reports protocol coverage
- Full support for SystemVerilog with VMM, VERA®, Verilog, and VHDL verification environments

Verification IP Components

- AMBA 3 AXI Master, Slave Monitor and Interconnect
- AMBA 2.0 AHB/APB Master, Slave, Monitor

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