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The CX4000 Structured ASIC product family is targeted at the mid-volume ASIC market. Manufactured in UMC’s 0.25um, 5-layer metal CMOS process, the CX4000 combines the reliability and quality of an industry-leading silicon foundry, with the high performance, low power consumption, and fast design turnaround time of ChipX’s Structured ASIC technology. The CX4000 family is applicable to ground-up digital ASIC designs, FPGA replacements, and obsolete component re-targeting projects.
Structured ASIC technology uses just two of the five available metal layers to program the logic, memory, I/O and clocking of an ASIC design and so eliminates the large costs of the remaining “fixed” masks. Wafers are manufactured up to Metal 3, where they are held pending the completion of the customer application. Completed chips can be delivered to the customer less than three weeks after sign-off of the finished design.
Structured ASIC technology is very similar in concept to FPGA, which makes it easy to use and familiar to most ASIC and system designers. Using metal interconnect segments rather than SRAM cells to program the ASIC, our technology reduces the area of the chip by between 5x and 10x over the equivalent FPGA and brings performance up to 90% of standard cell design speeds.
KEY FEATURES AND BENEFITS
* Structured ASIC architecture
* Low NRE and start-up costs
* Fast time to production
* 20K to 550K ASIC gates (~1.6M FPGA gates)
* Up to 448Kbits of fast block memory
* 2ns access time single-port SRAM, dual-port SRAM and ROM
* Low power consumption (0.1uW/MHz/Gate)
* 150 MHz core logic operation
* PCI, USB1.1, and LVDS up to 500Mbps
* 3.3V or 2.5V or mixed supply voltage operation
* Up to 1024 total pads
* 4 low jitter analog PLLs with internal loop filter
* Vast packaging library
* Standard ASIC tool flow
* Available front-end and FPGA conversion design services
* BIST and Scan synthesis test options
* Excellent for SoC designs, new ASICs, FPGA conversion, and obsolete device replacement