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The CX5000 System Slice is designed to be the SoC platform gate array of choice, offering a range of eight options. At the low end, the 189-pad CX50041 delivers 44K gates and 64K bits fast SRAM/ROM. The largest device, the 1089-pad CX51761, has 1.8M gates and 2.6M bits memory plus many useful PLL and DLL macros.
For memory-loaded designs, ChipX has configured a second CX5000 product line, known as the ‘Memory Pig.’ Available in four versions, and again including combinations of PLLs, DLLs, and high-speed I/O cells. Memory Pig devices are available with between 1.0 and 4.5M bits of memory with a memory to logic gate ratio of over 500%.
KEY FEATURES & BENEFITS
* Structured ASIC architecture
* Low NRE and start-up costs
* Fast time to production
* 44K to 1.8M usable ASIC gates
* Up to 4.5M bits of fast block memory
* 2ns access time single-port SRAM, dual-port SRAM and ROM
* Low power consumption (0.06uW/MHz/Gate)
* 200 MHz general core logic operation, 500 MHz in constrained clock domains
* PCI, PCI-X, SSTL, HSTL, USB1.1, lvPECL and LVDS up to 622 Mbps
* 1.5V or 1.8V or mixed supply voltage operation
* Up to 1100 total pads
* Low-jitter analog PLLs macro with internal loop filter
* Vast packaging library
* Standard ASIC tool flow
* Available front-end and FPGA conversion design services
* BIST and Scan synthesis test options
* Excellent for SoC designs, new ASICs, and FPGA conversion
The CX5000 System Slice design libraries are available now for download from the ChipX website (www.chipexpress.com). ChipX can also accept Memory Pig design handoffs. Design NREs range from $35K to $100K depending on the design service needs of each application. Unit pricing for devices at a 100K/year run rate vary from under $2 to about $60 subject to device size, packaging and test requirements.