NXP 150 MHz, 32-bit Cortex-M4 /Cortex-M0 DSC... by NXP

Semiconductor Vendor with ARM Processor RTL license from ARM

Product Description

First asymmetrical, dual-core digital signal controller featuring Cortex-M4 & Cortex-M0

A dual-core architecture and a unique set of configurable peripherals make it possible to develop DSP and MCU applications within a single architecture and development environment.

Key features
180 MHz, 32-bit ARM Cortex-M4
-180 MHz, 32-bit ARM Cortex-M0 coprocessor
-Up to 1 MB dual-bank Flash
-Up to 264 KB SRAM
-Up to 4 KB EEPROM
-Memory Protection Unit (MPU)
-Two high-speed USB 2.0 interfaces, with on-chip high-speed PHY
-10/100T Ethernet MAC with MII and RMII interfaces
-LCD controller with 1024 x 768 pixel display resolution
-Innovative Quad SPI Flash Interface (SPIFI)
-State Configurable Timer (SCT) Subsystem
-Configurable Serial GPIO
-Two CAN 2.0B
-AES Decryption with 128-bit secure OTP key storage
-Up to 164 GPIO
-Pin-compatible with the LPC1800 series

Additional features
-8-channel GPDMA controller
-Two 8-channel, 400 Ksps 10-bit ADCs and one 10-bit DAC
-Motor Control PWM and Quadrature Encoder Interface
-Four UARTs, smart card interface
-Two Fast-mode I2C, two I2S, three SSP/SPI
-Temperature range: –40 to +85 ºC

High Performance and Lower Power

Combined with large accelerated Flash and SRAM memories
and a set of unique configurable peripherals, the 150 MHz
LPC4300 enables customers to develop a wide range of
applications such as motor control, power management, industrial automation, robotics, medical, automotive accessories and embedded audio.

Combining MCU and DSP capabilities

The Cortex-M4 processor combines the benefits of a
microcontroller – integrated interrupt control, low power
modes, low cost debug and ease of use – with highperformance
digital signal processing features such as single-cycle MAC, single instruction multiple data (SIMD) techniques, saturating arithmetic, and a floating point unit. A Cortex-M0 coprocessor offloads many of the data movement and I/O handling duties that can drain the bandwidth of the Cortex-M4 core. This allows the Cortex-M4 to concentrate fully on crunching numbers for digital signal control applications.