EDANet Partner Program
The goal of ARM's Artisan EDANet Program is to ensure top-quality and extensive support for the IC design tools and flows used by our mutual customers using ARM Physical IP.For further questions or to join this program, please send an email to EDANet@arm.com.
EDANet
- Aldec
- Apache Design, Inc., A subsidiary of ANSYS, Inc.
- Atrenta Inc.
- GenSys(R)
- SpyGlass
- SpyGlass
- SpyGlass(R) CDC
- SpyGlass(R) Constraints
- SpyGlass(R) DFT
- SpyGlass(R) Physical
- SpyGlass(R) Power
- Genesys Testware
- IBM (International Business Machines)
- Legend Design Technology, Inc.
- Mentor Graphics Corporation
- Calibre® CMPAnalyzer
- Calibre® DESIGNrev™
- Calibre® InRoute™
- Calibre® Interactive
- Calibre® LFD™
- Calibre® nmDRC
- Calibre® nmLVS
- Calibre® PERC™
- Calibre® RealTime
- Calibre® RVE™
- Calibre® xACT 3D
- Calibre® xRC
- Calibre® YieldAnalyzer
- Calibre® YieldEnhancer
- Codelink
- Emulation Systems
- inFact Intelligent Testbench Automation
- iSolve Application Solutions
- Olympus-SoC™
- Precision Synthesis
- Questa inFact
- Questa Verification IP
- Questa Verification Platform
- Tessent Diagnosis - Diagnosis-Driven Yield Analysis
- Tessent MemoryBIST
- Tessent TestKompress - ATPG with Embedded Compression
- Transaction-based Simulation Acceleration
- Veloce
- Veloce Codelink
- Vista
- Sonics, Inc.
- Synopsys
- ARM-Synopsys Implementation Reference Methodology
- CHIPit Automated FPGA-based Prototyping Systems
- DesignWare Cores
- DesignWare System-Level Library
- Eclypse™ Low Power Solution
- FPGA Implementation
- HAPS Family of High-performance ASIC Prototyping Solutions
- Lynx Design System
- MVSIM
- Platform Architect
- Platform Architect
- RTL Verification IP
- Synopsys Professional Services
- VCS Functional Verification Solution
- VCS-CustomSim Mixed-Signal Verification
- Virtual Prototyping
- Virtual Prototyping for Android-based Products
- VMM Verification Methodology
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