CAMBRIDGE, UK– NOV 10, 2010 – ARM today introduced at the ARM Technology Conference, Santa Clara CA., the CoreLink™ 400 series of AMBA® 4 protocol-compliant system IP, enabling system designers to realize the full potential of the latest high-performance CPU and GPU technology. The CoreLink 400 series maximizes the performance and efficiency for SoC compute systems required by advanced mobile, consumer and enterprise applications.
The CoreLink 400 series perfectly complements the new ARM Mali™-T604 and Cortex™ -A15 high performance processors, designed for complex SoCs featuring clusters of multicore processors. CoreLink 400 system IP enables designers to resolve the critical issues of coherency, virtualization, latency and power management to ensure each processor is able to share memory resources and maximize overall system performance.
“We realise that building complex, many-core multimedia-rich compute sub-systems with the associated low latency, non-blocking memory sub-systems is challenging.” said Michael Dimelow, Marketing Director, processor Division, ARM. “The software community wants certainty when designing for these complex SoC designs. The good news is that the new CoreLink 400 series products provide hardware assistance in just the right places to really improve consistency and portability.”
The high-performance CoreLink CCI-400 Cache Coherent Interconnect enables the efficient sharing of the Cortex-A15 cache data with the Mali-T604 GPU, maximising throughput in a compute sub-system. The CCI-400 also significantly reduces the software overhead associated with cache maintenance and minimizes latency and power consumption by reducing off-chip memory transactions.
The CoreLink 400 series also includes a new fully configurable, non-blocking, lower latency, lower power NIC-400 Network Interconnect. The interconnect has support for Quality of Service and introduces Virtual Networks to ensure the GPU gets the bandwidth required and minimizing latency for the CPU. It also adds Thin Links to reduce wiring congestion.
The new CoreLink DMC-400 Dynamic Memory Controller provides a multi-channel, high-performance interface to the full specification of Low Power DDR2 (LPDDR2) and DDR3 memory systems. The DMC-400 together with the NIC-400 and CCI-400 provides end-to-end quality of service, using an enhanced priority-driven scheduler that exploits the maximum effective bandwidth of the memory interface.
The Cortex-A15 processor is the first ARM processor to feature full hardware assisted virtualization. To extend this capability across the complete SoC, the new CoreLink MMU-400 Memory Management Unit provides hardware accelerated memory translation for other virtualized masters.
The ARM CoreLink 400 series products are available for licensing today. For more information about the ARM CoreLink system IP, please visit: http://www.arm.com/products/system-ip/amba/index.php
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