At 130nm and below, wires dominate the performance and present a host of signal integrity problems to be solved in order to achieve first silicon success. The upgraded ARM-Cadence Reference Methodology, based on the Cadence® Encounter digital IC platform, provides an integrated, wire-centric RTL-to-GDSII implementation for ARM Partners.
The Encounter platform integrates new generation technology for wire-centric design with RTL Compiler for synthesis, First Encounter for silicon virtual prototyping, NanoRoute™ for signal-integrity aware routing, CeltIC™ and VoltageStorm™ for signal-integrity signoff. This upgraded release of the Reference Methodology enables customers to achieve improved QoS, the new metric of silicon quality, measured after wires for accuracy.
“The ARM-Cadence Encounter Reference Methodology is now available in limited release for some ARM9™ family cores. This release delivers significant performance results over the current Cadence methodology as a result of the addition of Encounter RTL Compiler,” said John Goodenough, global methodology manager, ARM. “This open collaboration demonstrates the commitment of ARM and Cadence to increase the access to new-generation nanometer solutions for our mutual customers.”
The new-generation technology behind Encounter RTL Compiler delivers global optimization for timing closure using a patented set of global focus algorithms that produce outstanding results at each stage of implementation including a better starting point for routing complex, wire-centric designs. Encounter RTL Compiler is used throughout the silicon design chain by application-specific integrated circuit (ASIC) and intellectual property (IP) vendors, and IC designers to help increase overall chip speed, and can help to reduce turnaround time.
“The momentum of the ARM-Cadence alliance in the past year has given ARM Partners an open choice of solutions and an open path to the future. Today, using the upgraded Reference Methodology, our mutual customers will be able to achieve outstanding quality of silicon in less time,” said Jan Willis, senior vice president of industry marketing, Cadence Design Systems. “Our collaboration with ARM will continue to focus on new-generation technology, open standards and optimizing the silicon design chain to deliver the critical solutions needed for nanometer design.”
The reference methodology supports the ARM926EJ-S™ core, the ARM966E-S™ core, and the ARM946E-S™ core. The ARM-Cadence Encounter Reference Methodology with RTL Compiler is available in limited release from ARM.
ARM is the industry’s leading provider of 16/32-bit embedded RISC microprocessor solutions. The company licenses its high-performance, low-cost, power-efficient RISC processors, peripherals, and system-chip designs to leading international electronics companies. ARM also provides comprehensive support required in developing a complete system. ARM’s microprocessor cores are rapidly becoming a volume RISC standard in such markets as portable communications, hand-held computing, multi-media digital consumer and embedded solutions. More information on ARM is available at http://www.arm.com/.
Cadence, the Cadence logo and First Encounter are registered trademarks of Cadence Design Systems. Encounter, NanoRoute, CeltIC and VoltageStorm are trademarks of Cadence Design Systems, Inc. in the U.S. and other countries.
ARM is a registered trademark of ARM Limited. ARM9, ARM926EJ-S, ARM946E-S and ARM966E-S are trademarks of ARM Limited. "ARM" is used to represent ARM Holdings plc (LSE: ARM and Nasdaq: ARMHY); its operating company ARM Limited; and the regional subsidiaries ARM INC; ARM KK; ARM Korea Ltd; ARM Taiwan; ARM France SAS; ARM Consulting (Shanghai) Co. Ltd.; and ARM Belgium N.V.
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