Power integrity analysis of an ARM Cortex-A15 quad core hard macro

The Seahawk hard macro is a Quad-core ARM® Cortex®-A15 implemented in the TSMC 28hpm process. It is designed to operate at frequencies close to 2 GHz & has DVFS & retention capabilities built in. This presentation describes the power integrity checks that were performed on the design to ensure proper functioning and reliability.

Who should attend:

VLSI design engineers involved in the back end flow will find this talk of interest. An understanding of sub-micron Power integrity challenges is recommended.

Presenter: Antony Sebastine, Staff Design Engineer, ARM

Antony has worked in the Physical implementation team at ARM for the past 8 years and has been involved in the development of the Cortex-A8, Cortex-A15 & Cortex-A57 cores. Antony’s has worked in physical design and has been involved power grid design and integrity analysis tasks on these cores. Antony has a Masters in Computer Engineering from the University of Texas at Austin.