IEEE 17th European Test Symposium 2012
Venue:
L'Impérial Palace
Location:
Allée de l'Impérial. 74000 Annecy. France
Date:
28 May 2012 - 01 June 2012
Room/Booth/Stand:
ARM has a very rigorous approach to reducing systems failures. At ETS ARM will be presenting and discussing its procedures and checks to ensure the highest level of fault robustness for the increasing number of complex and safety critical applications.
| Speaker | Title and Abstract | Date |
|---|---|---|
| Pete Harrod | Tutorial: “Dependable Processor Design” - http://ets2012.imag.fr/tutorials.php | Monday, May 28th , 2012, 14:00-18:30 |
Pete Harrod | Panel Session: “The impact of functional safety standards in the design and test of reliable and available integrated circuits” - Session 8A -http://ets2012.imag.fr/program.php | Thursday, May 31st, 2012, 11.00 - 12.30 |
| Teresa McLaurin | Vendor Session: Parallel MBIST and the ARM MBIST interface | Session 5C Wednesday, May 30th 2012, 11:00 - 12:30 |
| Michaela Gautier | Workshop on Processor Verification, Test and Debug (IWPVTD) The key objective of this workshop, planned to be held in conjunction with the European Test Symposium, is to provide an informal forum for vigorous creative discussion and debate of Processor Verification, Test and Debug. The aim is to encourage the presentation and discussion of innovative ideas that may not yet have been fully developed for presentation at reviewed conferences to address these challenges. Additionally, the workshop invites embedded talks and tutorials on cutting edge topics related to processor test, verification, debug and reliability. | Workshop: Thursday 31st May 2012 at 16:00 Friday 1st June 2012 at 16:00 |
