Optimize power and performance requirements while reducing time to market with Artisan 40nm physical IP

19 April 2011

Venue: Webinar
Location: Webinar

Time: 8:00 AM PDT

Register Now!


In today’s design environment being first to market is one of your strongest tools to gain the upper hand against the competition. However, with the increase in SoC design complexity fueled by the consumer’s insatiable appetite for higher performance and longer battery life in their devices, design cycles are rapidly expanding. How can you optimize your SoC for performance and battery life without extending your design cycle? How can you leverage the latest processor technologies to satisfy the consumer’s demand for feature rich devices? And how do you ensure silicon manufacturing that is right the first time?

This webinar will detail best-in-class strategies for designing optimized SoCs using silicon proven ARM®Artisan® Physical IP for TSMC’s 40nm G / LP manufacturing processes. This session will demonstrate cost-effective techniques for designing performance driven consumer devices requiring advanced functionality without increasing power consumption. We will also cover enabling higher levels of technology innovation, while maintaining power budgets in performance driven consumer devices such as disc drives, set-top boxes, mobile computing devices, networking applications, high-definition televisions and graphic processors.

The session will cover:

  • Obtaining a high degree of flexibility through multi channel Logic libraries.
  • Enabling significant power and cost savings by replacing or complementing the HVt, RVt or LVt implant layers with long channel length devices providing better performance, lower leakage and reduced manufacturing costs.
  • Utilizing advanced embedded memory compilers and interface IP to meet a wide range of performance, power and area requirements.
  • Reducing both dynamic and leakage power in SoC designs
  • Leveraging superior ARM CPU implementation, unavailable in non-processor optimized solutions with Artisan high density memories coupled with ARM’s innovative high speed architecture and multiple processor-specific low power management modes.

Attend this webinar to gain a thorough understanding of:

  • Best-in-class practices for managing your power and performance envelopes
  • Benefits of ARM’s Artisan 40nm G IP platform
  • Effective methods of leveraging ARM processor and physical IP for superior ARM CPU implementation

Who should attend?

  • Design engineers and team leads designing SoC on TSMC 40nm process.
  • Embedded memory design teams

Don’t miss out, register today