Common Platform Technology Forum

Join us at the Common Platform Technology Forum and learn more about how ARM is collaborating with Globalfoundries, IBM and Samsung to deliver a proven path to silicon on leading Common Platform process technologies including 90nm, 65nm, 45nm, 32nm and 28nm.

The Common Platform Technology Forum will focus on access to industry ready technology, proven design solutions and advanced technologies for high growth markets such as mobile and low power. Technical details of the innovative 28nm HKMG design for low-power applications will be revealed, along with technology advancements in SoC enablement solutions, materials science, process technology and manufacturing.

Live Event + Online Event
This year’s forum offers the industry a live event as well as an online event for those not able to attend in person. Visit www.commonplatform.com for more details and to register.


ARM Activities

Industry Keynote – Mike Muller, Chief Technology Officer, ARM 10:30am

Technical Breakout
2:00 – 2:40pm – IP Development from the Ground Up, Rob Aiken, Fellow, ARM
As process technology continues to advance, chip design is becoming increasingly challenging. Design must consider nanometer scale effects in terms of lithography, variability, and so on while simultaneously meeting performance, power and area (PPA) targets across tens or hundreds of millions of transistors. This session will discuss best in class design solutions to address these challenges.

Panel
2:50 – 3:30pm – Design Enablement, John Heinlein, Vice President, Physical IP Division, ARM

ARM Booth
Exhibit Hours: 11:30am – 6:00pm
See demos for the following products, ready for Common Platform’s process technology:

• 1.5 GHz Cortex-A9 test chip
• DesignStart comprehensive offering of free standard and logic, memory and interface IP
• 32nm / 28nm optimized physical IP for Common Platform HKMG technology

And find out how our collaboration with the Common Platform™ (IBM, Samsung and GLOBALFOUNDRIES) and leading EDA partners accelerate your path to silicon on leading-edge system-on-chip advanced node design.